1. Field of the Invention
The present invention relates to a digital television DTV, and more particularly to a down conversion decoding device of the DTV differentially applying a memory according to a type of a picture upon a down conversion.
2. Discussion of Related Art
Generally, a picture compressing and restoring technique for a moving picture experts group MPEG has been becoming an essential technique in the multi-media age, and has been a standard of a digital versatile disc DVD and a digital television DTV, etc.
At present, the MPEG compressing and restoring of a high definition HD degree has been considered as the standard or a real standard in the DTV.
This means that an existing analog television of NTSC, etc., is increasingly being substituted by the digital television.
However, it is estimated that demand for the analog television of a standard definition SD degree will be lasted for a long time due to a high price of the high definition television HDTV during the NTSC type analog television is completely substituted with the HDTV.
Here, the SDTV does not display a signal of the HDTV on a monitor of the HD degree, but down-converts a HD signal to display it on the popularized monitor of the SD degree. That is, it means the TV displaying (the down-converted HD signal) on the NTSC TV or a settop box, and also, it can receive the signal of the SD degree.
For example, the SDTV can lower the HD signal of a 1920xc3x971080 60 Hz interlaced scanning method to the SD signal a 720xc3x97480 60 Hz interlaced scanning method to display it, and also, can display the SD signal of the 720xc3x97480 60 Hz interlaced scanning method without conversion.
However, the MPEG-2 is generally being used as a compressing method of the DTV signal, and the compressing method applying the MPEG-2, that is, a grand-alliance method, was adopted in U.S.A, but, the problem of this method is that the signal of the HDTV is not scalable based upon an MP@HL of the MPEG-2.
Here, the scalable picture compressing method can largely be applied in a spatial domain, a temporal domain and a signal-to-noise ratio SNR domain.
At this time, the SDTV requires a scalability in the spatial domain, which make it possible for the receiver to perform a desired reception according to the display size thereof, by adding a bit stream which compressed a different signal between the HD signal and SD signal to the SD bit stream after selecting the signal of the SD degree in signals of the HD degree to make a firstly compressed bit stream, upon compression of the HDTV signal.
Meanwhile, the signal type of the grand-alliance is not scalable and therefor, the receiver regularly performs a decoding upon displaying the HD signal to the HD degree, but, it requires a special method capable of down-converting the HD signal to the SD upon displaying the HD signal to the SD degree.
On the other hand, there is no an algorism set in the MPEG and grand-alliance standard and therefor, a TV receiver manufacturer is using his own method.
In FIG. 1 showing a block diagram of a video decoding device of the DTV, a video decoding device 10 is formed of: a variable length decoding VLD unit 11 variable length decoding a discrete cosine transform DCT coefficients and a motion vector MV, etc., in a bit stream which was compressed and transmitted to output it; an inverse scan unit 12 inversely scanning the DCT coefficients decoded in the VLD unit 11; an inverse quantization unit 13 inversely quantizing the inversely scanned DCT coefficients; a 8xc3x978 inverse discrete cosine transform IDCT unit 14 performing the inverse discrete cosine transform for values inversely quantized in the inverse quantization unit 13 to output them as spatial pixel values; a frame memory unit 15 storing standard frames; a motion compensation unit 16 reading pixel values from the frame memory unit 15 to compensate movement with motion vectors MV output from the VLD unit 11; and an adder 17 adding the value obtained from the motion compensation unit 16 and pixel value converted in the 8xc3x978 IDCT unit 14 to decode it to an original pixel. Here, an output of the adder 17 is input to the frame memory unit 15 to be stored.
In the video decoding device 10 having the aforesaid configuration, the VLD unit 11 valid length decodes the DCT coefficient and the motion vector, etc., in the compression bit stream to be input to output them.
And, the inverse scan unit 12 inversely scans the DCT coefficients decoded in the VLD unit 11 and after that, inversely quantizes them through the inverse quantization unit 13 to output them to the 8xc3x978 IDCT unit 14.
The 8xc3x978 IDCT unit 14 performs the IDCT for the inversely quantized values to transform them to the spatial values and after that, outputs the transformed values to the motion compensation unit 16.
The motion compensation unit 16 reads pixel value from the frame memory unit 15 according to the motion vectors MV output from the VLD 11 and the frame mode to compensate the motion and after that, outputs it to the adder 17. The adder 17 adds the value obtained from the motion compensation unit 16 and pixel value transformed in the 8xc3x978 IDCT unit 14 to output it. At this time, an output of the adder 17 is fedback to the frame memory unit 15 to be stored.
Here, for an frame I, the motion compensation is not used and the decoding is performed only by the IDCT, but, for a P frame and a B frame, decoding performed while the motion compensation is used, together with the IDCT.
To down-convert the HD signal output from the decoding device of the DTV to the SD degree, the IDCT part and the motion compensation part are all changed, and the size of the frame memory of the frame memory unit 15 is changed according to the algorism.
Generally, the frame memory is classified into a full-memory version, a half-memory version and a quarter-memory version according to the size thereof, and each of them performs the decoding as the following Table 1.
Each memory version shown in the aforesaid Table 1 will be explained with reference to attached FIGS. 2 to 4.
First, in FIG. 2 which is a block diagram of the decoding device in case of the full-memory version upon general down conversion, the decoding device of FIG. 2 is formed of the HDTV decoder 10, horizontal low pass filter LPF 20, horizontal xc2xd down sampling unit 30, a vertical LPF unit 40, and a vertical xc2xd down sampling unit 50.
In FIG. 2, when the frame memory unit 15 is the full-memory version, the HDTV decoder 10 has the configuration as shown in FIG. 1, and the picture of the HD degree output from the HDTV decoding unit 10 is input to the horizontal LPF unit 20, and a low pass filtering is horizontally performed.
After that, filtered data is horizontally xc2xd decimated through the horizontal xc2xd down sampling unit 30.
And, data horizontally decimated in half is vertically low pass filtered through the vertical LPF unit 40 and after that, is vertically decimated in half through the vertical xc2xd down sampling unit 50.
At this point, the full-memory version may obtain the highest quality of video, but, since the required size of the frame memory is the same as the HDTV and also, the horizontal and vertical low pass filtering are required after the HD decoding, a hardware is more complicate than the HDTV receiver and accordingly, it is generally used only as a Benchmark comparing performance of different HDTV down conversion algorisms.
FIG. 3 is a diagram showing a down sampling operation using a general filter, and FIG. 4 is a block diagram of the decoding device in case of the half-memory version during the general down conversion.
The half-memory version performs the decoding to the picture smaller size than the HD degree upon decoding the HD bit stream, for solving the complexity of the full-memory version.
In other words, the decoding device in case of the half-memory version as shown in FIG. 4 has the VLD unit 11, the inverse scan unit 12 and the inverse quantizing unit 13 as shown in FIG. 1, and inversely discrete cosine transforms only a part of the inversely quantized 8xc3x978 DCT coefficient through a filtering and 4xc3x978 IDCT unit 41, thereby performing the down sampling.
The filtering and 4xc3x978 IDCT unit 41 is formed of a filter 34 discarding a part of a horizontal high frequency part as shown in FIG. 3b, and a 4xc3x978 IDCT unit 35 performing the IDCT for an output of the filter unit 34. Here, the filter 34 may be referred to as a zonal filter.
For example, if 8xc3x978 IDCT coefficient is input to the general 8xc3x978 IDCT unit 14 as shown in FIG. 3a, 8xc3x978 pixel values may be obtained, but, if it is input to the filtering and 4xc3x978 IDCT unit 41 as shown in FIG. 3b, the filter unit 34 leaves only 4xc3x978 part corresponding to a horizontal low frequency part and discards the rest high frequency part, thereby performing the down sampling. And, if the rest 4xc3x978 IDCT coefficient is input to the 4xc3x978 IDCT part 35 and 4xc3x978 IDCT is then performed, only 4xc3x978 pixel values are obtained. As a result, we can know that the 8xc3x978 IDCT coefficient is horizontally down-sampled in half while passing the 4xc3x978 IDCT unit 41.
Since the size of the picture is reduced through the horizontal xc2xd down sampling, the motion vectors are input to the motion compensation unit 43 after being respectively scaled according to the reduced size in the vector scaling unit 43.
The motion compensation unit 43 performs the motion compensation of the half-memory version with the motion vectors which were scaled in the motion vector scaling unit 43 to be output.
Further, in case of the quarter-memory version, only 4xc3x974 part corresponding to the low frequency part in the 8xc3x978 IDCT coefficient is left and the rest are discarded, through the filter upon the decoding. And, the 4xc3x974 IDCT is performed only with the rest 4xc3x974 parts, thereby obtaining 4xc3x974 pixel values. Resultingly, the aforesaid shows that xc2xd down sampling is horizontally and vertically performed.
If the horizontal and vertical xc2xd down sampling are performed, the size of the picture is reduced and therefore, the motion vectors are respectively scaled correspondingly to the size thereof through the motion vector scaling.
That is, in the quarter-memory version, the size of the frame is reduced in half on the horizontal axis and vertical axis and therefor, the motion vector has to be scaled in half on the horizontal axis and vertical axis as MVx/2 and MVy/2 of the Table 1.
As mentioned above, the conventional down conversion decoding device is divided according to the size of the frame memory, and the capacity thereof is largely changed as whether an input signal is the interlaced scanning or a sequential scanning. In case of the interlaced scanning, the half-memory version exhibits the capacity corresponding to the full-memory version, but, the capacity of the quarter-memory version is insufficient. Furthermore, in case of the quarter-memory version, the memory may be reduced in the decoding device but, a format transform unit (not shown) connected to a rear part of the decoding unit requires many additional memory for the interlacing.
And, in case of a moving picture that a display format is the sequential scanning, the quarter-memory version shows a pretty good capacity, but on the other hand, in case that it is the interlaced scanning, there are many problems. Accordingly, to improve the capacity of the quarter-memory version, an interpolation of a high order is performed, but, since the major part of information was lost upon the filtering, there is a problem that the quality of the picture is deteriorated.
Accordingly, the present invention is directed to a down conversion decoding device of a digital television that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a down conversion device of a digital television reducing a size of a memory by changing a use of a memory according to a type of a picture upon a down conversion.
Another object of the present invention is to provide a down conversion device of a digital television capable of enhancing an picture quality by using a discrete cosine transform coefficient discarded through a filtering for an interpolation upon a motion compensation.
Further another object of the present invention is to provide a down conversion decoding device of a digital television easily performing an interlacing function through a down conversion.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a down conversion decoding device of a digital television in accordance with the present invention applies advantages of a half-memory version method and a quarter-memory version method with the characteristic of a compressing method of I, B and P frames.
In other words, since I and P frames are used standard frames for a motion compensation, they are decoded with the half-memory version, and the B frame is decoded with the quarter memory.
Thus, the down conversion decoding device of the digital television is formed of: an input signal processing unit decoding discrete cosine transform coefficient of bit stream to be input and motion vectors, etc., performing an inverse quantization and an inverse discrete cosine transform for only given coefficient after inversely scanning decoded discrete cosine transform coefficient; a motion compensation unit performing a motion compensation according to a type of the motion vector decoded in the input signal processing unit and the inversely discrete cosine transformed frame; a frame storing unit having different sizes according to characteristics of the input frame, and storing frames motion compensated in the motion compensation unit; and a format selecting unit filtering a corresponding frame stored in the frame storing unit according to a display format, or, outputting the corresponding frame as it is.
The input signal processing unit is formed of: a variable length decoding unit decoding the discrete cosine transform coefficient, forward motion vector and backward motion vector in compressed bit stream to output them; an inverse scanning and filtering unit inversely scanning discrete cosine transform coefficient decoded in the variable length decoding unit, leaving discrete cosine transform coefficient corresponding to a low frequency in inversely scanned discrete cosine transform coefficient, and discarding the rest coefficient of a high frequency part; an inverse quantization unit inputting discrete cosine transform coefficient corresponding to the low frequency left in the inverse scanning and filtering unit to quantize them; and an inverse discrete cosine transform unit inversely discrete cosine transforming discrete cosine transform values inversely quantized in the inverse quantization unit, and transforming them to spatial pixel values to output them.
The inverse scanning and filtering unit leaves only discrete cosine transform coefficient of 4xc3x978 part corresponding to a horizontal low frequency part in 8xc3x978 discrete cosine transform coefficients inversely scanned in the inverse scanning and filtering unit, and outputs the rest high frequency part to the motion compensation unit.
The inverse discrete cosine transform unit inputs inversely quantized 4xc3x978 discrete cosine transform values to perform 8xc3x978 IDCT.
The inverse discrete cosine transform unit performs 16xc3x978 discrete cosine transform to perform 8xc3x978 filtering, after collecting two horizontal 8xc3x978 blocks and performing 8xc3x978 inverse discrete cosine transform, respectively.
The motion compensation and frame storing units are formed of: a frame buffer storing I frame output from the input signal processing unit or a motion compensated P frame; a uni-directional motion compensation unit adding P frame coefficient values output from the input signal processing unit to the motion compensated pixel values to store it in the frame buffer, after compensating the motion with the forward motion vector output from the input signal processing unit and the standard frame stored in the frame buffer; a bi-directional motion compensation unit compensating the motion with the forward motion vector and the backward motion vector output from the input signal processing unit, and with I and P frames stored in the frame buffer or two P frames; 4xc3x974 converting unit sub sampling 4xc3x978 coefficient of the B frame output from the input signal processing unit to 4xc3x974 coefficient to output it; and a B frame buffer adding pixel values motion-compensated in the bi-directional motion compensation unit and 4xc3x974 coefficient values converted in the 4xc3x974 converting unit to store them, and after that, outputting them.
The uni-directional and bi-directional motion compensation units analyze discrete cosine transform coefficient of the high frequency part discarded from the inverse scanning and filtering unit to determine an interpolation order.
In case that the frame output from the inverse quantizing unit is the B frame, a 4xc3x974 filtering and inverse discrete cosine transform unit is additionally provided instead of the 4xc3x978 IDCT unit and 4xc3x974 converting unit.
The picture quality can be enhanced while reducing the size of the memory required for the down decoding device of the digital television,.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.